(Hong Kong)
Product Summary
The 74HC373PW is a high-speed Si-gate CMOS device. It is pin compatible with low power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC standard no. 7A. The 74HC373PW is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The 74HC373PW consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches.
Parametrics
74HC373PW absolute maximum ratings: (1)propagation delay(CL=15pF; VCC =5V):Dn to Qn:12ns,LE to Qn:15ns; (2)input capacitance:3.5pF; (3)power dissipation capacitance per latch:45pF.
Features
74HC373PW features: (1)3-state non-inverting outputs for bus oriented applications; (2)Common 3-state output enable input; (3)Functionally identical to the “563”, “573” and “533”; (4)Output capability: bus driver; (5)ICC category: MSI.
Diagrams
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 74HC373PW |
NXP Semiconductors |
Latches OCTAL 3-STATE LATCH |
Data Sheet |
Negotiable |
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74HC373PW,112 |
NXP Semiconductors |
Latches OCTAL 3-STATE LATCH |
Data Sheet |
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74HC373PW,118 |
NXP Semiconductors |
Latches OCTAL 3-STATE LATCH |
Data Sheet |
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