(Hong Kong)
Product Summary
The 74HC273PW is a high-speed Si-gate CMOS device. It is pin compatible with low power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC standard no. 7A. The 74HC273PW has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
Parametrics
74HC273PW absolute maximum ratings: (1) propagation delay (CL=15pF; VCC =5V): CP to Qn: 15ns, MR to Qn: 20ns; (2) input capacitance: 3.5pF; (3) power dissipation capacitance per latch: 20pF for HC, 23pF for HCT; (4) maximum clock frequency: 66MHz for HC, 36MHz for HCT.
Features
74HC273PW features: (1) Ideal buffer for MOS microprocessor or memory; (2) Common clock and master reset; (3) Eight positive edge-triggered D-type flip-flops; (4) See “377” for clock enable version; (5) See “373” for transparent latch version; (6)See “374” for 3-state version; (7)Output capability; standard; (8)ICC category: MSI.
Diagrams
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 74HC273PW |
NXP Semiconductors |
Flip Flops OCTAL D-TYPE |
Data Sheet |
Negotiable |
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74HC273PW,112 |
NXP Semiconductors |
Flip Flops OCTAL D-TYPE |
Data Sheet |
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74HC273PW,118 |
NXP Semiconductors |
Flip Flops OCTAL D-TYPE |
Data Sheet |
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