TDA8007BHL

Product Summary

The TDA8007BHL is a cost-effective card interface for dual smart card readers. Controlled through a parallel bus, it meets all requirements of ISO 7816, GSM 11-11, EMV4.2 and EMV 2000. It is addressed on a non-multiplexed 8-bit databus, by means of address registers AD0, AD1, AD2 and AD3. The TDA8007BHL can be also addressed through a multiplexed access. The integrated ISO UART and the time-out counters allow easy use even at high baud rates with no real time constraints. Due to its chip select, external input/output and interrupt features, it greatly simplifies the realization of a reader of any number of cards. The TDA8007BHL gives the cards and the reader a very high level of security, due to its special hardware against ESD, short-circuiting, power failure, etc. The integrated step-up converter allows operation within a supply voltage range of 2.7 V to 6 V.

Parametrics

TDA8007BHL absolute maximum ratings: (1)VDD supply voltage: -0.5 to +6.5 V; (2)VDDA analog supply voltage: -0.5 to +6.5 V; (3)VI input voltage on pins SAM, SAP, SBM, SBP and VUP: -0.5 to +7.5 V; (4)on all other pins: -0.5 to VDD + 0.5 V; (5)Ptot total power dissipation Tamb = - 25 to +85℃: 700mW; (6)Tstg storage temperature: -55 to +150℃; (7)Tj junction temperature: 125℃.

Features

TDA8007BHL features: (1)Control and communication through an 8-bit parallel interface, compatible with non-multiplexed memory access, TDA8007BHL/C3 can be also addressed through a multiplexed memory access; (2)Specific ISO UART with parallel access input/output for automatic convention processing, variable baud rate through frequency or division ratio programming, error management at character level for T = 0 and extra guard time register; (3)FIFO for 1 to 8 characters in reception mode; (4)Parity error counter in reception mode and in transmission mode with automatic re-transmission; (5)Dual VCC generation: 5 V±5 %, 65 mA (max.); 3 V±8 %, 50 mA (max.) or 1.8 V±10 %, 30 mA (max.); with controlled rise and fall times; (6)Dual cards clock generation (up to 10 MHz), with three times synchronous frequency doubling (fXTAL, 12fXTAL, 14fXTAL and 18fXTAL); (7)Cards clock stop (at high or low level) or 1.25 MHz (from internal oscillator) for cards Power-down mode; (8)Automatic activation and deactivation sequence through an independent sequencer; (9)Supports the asynchronous protocols T = 0 and T = 1 in accordance with: ISO 7816 and EMV4.2; (10)Versatile 24-bit time-out counter for Answer To Reset (ATR) and waiting times processing; (11)Specific Elementary Time Unit (ETU) counter for Block Guard Time (BGT): 22 in T = 1 and 16 in T = 0.

Diagrams