TMS320C6748AZCE3

Product Summary

The TMS320C6748AZCE3 is a Low-power applications processor based on a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000 platform of DSPs. The TMS320C6748AZCE3 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The TMS320C6748AZCE3 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB Boot ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.

Parametrics

TMS320C6748AZCE3 absolute maximum ratings: (1)Supply voltage range: -0.5V to 1.4V; (2)Input voltage (VI) range: -0.3 V to CVDD + 0.3V; (3)Output voltage (VO) range: -0.5 V to DVDD + 0.3V; (4)Clamp Current: ±20mA; (5)Operating Junction Temperature ranges, Commercial (default): 0 to 90℃; (6)TJ Extended (A version): -40 to 105℃; (7)Storage temperature range, Tstg (default): -55 to 150℃.

Features

TMS320C6748AZCE3 features: (1)300-MHz C674x VLIW DSP; (2)C674x Instruction Set Features; (3)C674x Two Level Cache Memory Architecture; (4)Enhanced Direct-Memory-Access Controller 3 (EDMA3); (5)TMS320C674x Floating-Point VLIW DSP Core; (6)Software Support; (7)128K-Byte RAM Shared Memory; (8)1.8V or 3.3V LVCMOS IOs (except for USB and DDR2 interfaces); (9)32-Bit Load/Store RISC architecture; (10)4K Byte instruction RAM per core; (11)512 Bytes data RAM per core; (12)PRU Subsystem (PRUSS) can be disabled via software to save power; (13)Commercial or Extended Temperature.

Diagrams