Product Summary
The SN65LVDS301ZQER is a programmable 27-bit display serial interface transmitter. The SN65LVDS301ZQER converts 27 parallel data inputs to 1, 2, or 3 Sub Low-Voltage Differential Signaling (SubLVDS) serial outputs. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the SN65LVDS301ZQER adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30, 15, or 10 times the pixel-clock data rate depending on the number of serial links used. A copy of the pixel clock is output on a separate differential output.
Parametrics
SN65LVDS301ZQER absolute maximum ratings: (1)Supply voltage range, VDD(2), VDDPLLA, VDDPLLD, VDDLVDS: -0.3 to 2.175 V; (2)Voltage range at any output terminal: -0.5 to 2.175 V; (3)Voltage range at any input terminal: -0.5 to 2.175 V; (4)Human Body Model(3) (all Pins): ±3 kV; (5)Electrostatic discharge Charged-Device Mode(4)l (all Pins): ±500 V; (6)Machine Model(5) (all pins): ±200V; (7)Continuous power dissipation: See Dissipation Rating Table.
Features
SN65LVDS301ZQER features: (1)FlatLink 3G serial interface technology; (2)Compatible with FlatLink3G receivers such as SN65LVDS302 (product under preview); (3)Input supports 24-bit RGB video mode interface; (4)24-Bit RGB Data, 3 Control Bits, 1 Parity Bit and 2 Reserved Bits Transmitted over 1, 2 or 3 Differential Lines; (5)SubLVDS Differential Voltage Levels; (6)Effective Data Throughput up to 1755Mbps; (7)Three Operating Modes to Conserve Power; (8)Bus Swap for Increased PCB Layout Flexibility; (9)1.8-V Supply Voltage; (10)ESD Rating>2 kV (HBM); (11)Typical Application: Host-Controller to Display-Module Interface.
Diagrams
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![]() SN65LVDS301ZQER |
![]() Texas Instruments |
![]() Serializers & Deserializers (Serdes) Interface IC Programmable 27B Displ Ser Interface |
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