Product Summary

The 74HCT377N is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HCT377N is specified in compliance with JEDEC standard no. 7A. The 74HCT377N has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.

Parametrics

74HCT377N absolute maximum ratings: (1) propagation delay CP to Qn (CL = 15pF; VCC = 5V): 14ns; (2) fmax maximum clock frequency: 53MHz; (3) CI input capacitance: 3.5pF; (4) CPD power dissipation capacitance per flip-flop: 20pF.

Features

74HCT377N features: (1)Ideal for addressable register applications; (2)Data enable for address and data synchronization applications; (3)Eight positive-edge triggered D-type flip-flops; (4)See “273” for master reset version; (5)See “373” for transparent latch version; (6)See “374” for 3-state version; (7)Output capability: standard; (8)ICC category: MSI.

Diagrams

74HCT377N block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)		 Quantity
74HCT377N
74HCT377N
NXP Semiconductors
Flip Flops OCTAL D-TYPE W/ENABL
Data Sheet
Negotiable 
74HCT377N,652
74HCT377N,652
NXP Semiconductors
Flip Flops OCTAL D-TYPE W/ENABL
Data Sheet
0-1: $0.40
1-25: $0.35
25-100: $0.31
100-250: $0.27