Product Summary

The SN74LVC16373ADGGR is a 16-bit transparent D-type latch. It is designed for 1.65V to 3.6V VCC operation. The SN74LVC16373ADGGR is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The SN74LVC16373ADGGR can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

Parametrics

SN74LVC16373ADGGR absolute maximum ratings: (1)VCC Supply voltage range: –0.5 to 6.5 V; (2)VI Input voltage range(2): –0.5 to 6.5 V; (3)VO Voltage range applied to any output in the high-impedance or power-off state(2): –0.5 to 6.5 V; (4)VO Voltage range applied to any output in the high or low state(2) (3): –0.5 to VCC + 0.5V; (5)IIK Input clamp current VI < 0: –50mA; (6)IOK Output clamp current VO < 0: –50mA; (7)IO Continuous output current: ±50mA; (8)Continuous current through each VCC or GND: ±100mA; (9)θJA Package thermal impedance: 70℃/W; (10)Tstg Storage temperature range:–65 to 150℃.

Features

SN74LVC16373ADGGR features: (1)Member of the Texas Instruments Widebus Family; (2)Operates From 1.65V to 3.6V; (3)Inputs Accept Voltages to 5.5V; (4)Max tpd of 4.2ns at 3.3V; (5)Typical VOLP (Output Ground Bounce) <0.8V at VCC = 3.3V, TA = 25℃; (6)Typical VOHV (Output VOH Undershoot) > 2V at VCC = 3.3V, TA = 25℃; (7)Ioff Supports Partial-Power-Down Mode Operation; (8)Supports Mixed-Mode Signal Operation (5V Input and Output Voltages With 3.3V VCC); (9)Latch-Up Performance Exceeds 100mA Per JESD 78, Class II; (10)ESD Protection Exceeds JESD 22.

Diagrams

SN74LVC16373ADGGR block diagram

Image Part No Mfg Description Data Sheet Download Pricing
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SN74LVC16373ADGGR
SN74LVC16373ADGGR

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Data Sheet

0-1: $0.57
1-25: $0.45
25-100: $0.41
100-250: $0.35
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