Product Summary

The GC5328IZER is a Low power wideband digital Predistortion Transmit Processor. The GC5328IZER includes a digital upconverter (DUC) block, a crest factor reduction (CFR) block, a digital predistortion (DPD) block, feedback (FB) block, and capture buffer (CB) blocks. The applications of the GC5328IZER include 3 GPP (W-CDMA) Base Stations, 3 GPP2 (CDMA2000) Base Stations, WiMAX, WiBRO, and LTE (OFDMA) Base Stations, Multicarrier Power Amplifiers (MCPAs).

Parametrics

GC5328IZER absolute maximum ratings: (1)VDD, VDDA Core supply voltage: –0.3 to 1.32 V; (2)VDDS Digital supply voltage for TX: –0.3 to 2 V; (3)VDDSHV Digital supply voltage: –0.3 to 3.6 V; (4)VIN Input voltage (under/overshoot): –0.5 to VDDSHV + 0.5 V; (5)Clamp current for an input/output: –20 to 20 mA; (6)Tstg Storage temperature: –65 to 150℃; (7)Lead soldering temperature, 10 seconds: 300℃; (8)ESD classification Class 2 (Required 2-kV HBM, 500-V CDM); (9)(Passed 2.5-kV HBM, 500-V CDM, 200-V MM); (10)Moisture sensitivity Class 3 (floor life at 30℃/60% H): 1 week; (11)Reflow conditions JEDEC standard: 260℃; (12)Latchup JEDEC Level 2 per JEDEC 78 standard (at 90℃ and 1.5× Vmax): ±100mA.

Features

GC5328IZER features: (1)Integrated DUC, CFR, and DPD Solution; (2)20-MHz Max. Signal Bandwidth, Based on Max. DPD Clock of 200 Mhz, Fifth-Order Correction; (3)DUC: Up to 12 CDMA2000/TDSCDMA, 4W-CDMA, 2?0 MHz or 1?0 MHz OFDMA carriers; (4)CFR: Typically Meets 3GPP TS 25.141< 6.5dB PAR, <8.5dB PAR for OFDMA signals; (5)DPD: Short-Term Memory Compensation, Typical ACLR Improvement > 20 dB; (6)GC5328IZER PBGA Package, 23 mm x23 mm; (7)1.2-V Core, 1.8-V HSTL, 3.3-V I/O; (8)2.5-W Typical Power Consumption; (9)TMS320C6727 DPD Optimization Software.

Diagrams

GC5328IZER block diagram

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